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| 80C186EA 80C188EA AND 80L186EA 80L188EA 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y Y Y Y 80C186 Upgrade for Power Critical Applications Fully Static Operation True CMOS Inputs and Outputs Y Integrated Feature Set Static 186 CPU Core Power Save Idle and Powerdown Modes Clock Generator 2 Independent DMA Channels 3 Programmable 16-Bit Timers Dynamic RAM Refresh Control Unit Programmable Memory and Peripheral Chip Select Logic Programmable Wait State Generator Local Bus Controller System-Level Testing Support (High Impedance Test Mode) Speed Versions Available (5V) 25 MHz (80C186EA25 80C188EA25) 20 MHz (80C186EA20 80C188EA20) 13 MHz (80C186EA13 80C188EA13) Speed Versions Available (3V) 13 MHz (80L186EA13 80L188EA13) 8 MHz (80L186EA8 80L188EA8) Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Supports 80C187 Numeric Coprocessor Interface (80C186EA only) Available in the Following Packages 68-Pin Plastic Leaded Chip Carrier (PLCC) 80-Pin EIAJ Quad Flat Pack (QFP) 80-Pin Shrink Quad Flat Pack (SQFP) Available in Extended Temperature Range ( b 40 C to a 85 C) Y Y Y Y Y The 80C186EA is a CHMOS high integration embedded microprocessor The 80C186EA includes all of the features of an ``Enhanced Mode'' 80C186 while adding the additional capabilities of Idle and Powerdown Modes In Numerics Mode the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor 272432 - 1 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata October 1995 COPYRIGHT INTEL CORPORATION 1995 Order Number 272432-003 1 80C186EA 80C188EA 80L186EA 80L188EA 80C186EA 80C188EA AND 80L186EA 80L188EA 16-Bit High Integration Embedded Processor CONTENTS INTRODUCTION 80C186EA CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EA PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit DMA Control Unit Chip-Select Unit Refresh Control Unit Power Management 80C187 Interface (80C186EA Only) ONCE Test Mode DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA Pinout Compatibility Operating Modes TTL vs CMOS Inputs Timing Specifications PACKAGE INFORMATION Prefix Identification Pin Descriptions 80C186EA Pinout PAGE 4 4 4 4 5 5 5 7 7 7 7 8 8 8 8 8 8 8 9 9 9 15 CONTENTS PACKAGE THERMAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Recommended Connections DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation AC SPECIFICATIONS AC Characteristics 80C186EA20 13 AC Characteristics 80L186EA13 8 Relative Timings AC TEST CONDITIONS AC TIMING WAVEFORMS DERATING CURVES RESET BUS CYCLE WAVEFORMS EXECUTION TIMINGS INSTRUCTION SET SUMMARY REVISION HISTORY ERRATA PAGE 20 21 21 21 22 24 24 25 25 27 29 30 30 33 33 36 43 44 50 50 2 2 80C186EA 80C188EA 80L186EA 80L188EA NOTE Pin names in parentheses apply to the 80C186EA 80L188EA Figure 1 80C186EA 80C188EA Block Diagram 3 3 272432- 2 80C186EA 80C188EA 80L186EA 80L188EA INTRODUCTION Unless specifically noted all references to the 80C186EA apply to the 80C188EA 80L186EA and 80L188EA References to pins that differ between the 80C186EA 80L186EA and the 80C188EA 80L188EA are given in parentheses The ``L'' in the part number denotes low voltage operation Physically and functionally the ``C'' and ``L'' devices are identical The 80C186EA is the second product in a new generation of low-power high-integration microprocessors It enhances the existing 80C186XL family by offering new features and operating modes The 80C186EA is object code compatible with the 80C186XL embedded processor The 80L186EA is the 3V version of the 80C186EA The 80L186EA is functionally identical to the 80C186EA embedded processor Current 80C186EA customers can easily upgrade their designs to use the 80L186EA and benefit from the reduced power consumption inherent in 3V operation The feature set of the 80C186EA 80L186EA meets the needs of low-power space-critical applications Low-power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation Minimum current consumption is achieved by providing a Powerdown Mode that halts operation of the device and freezes the clock circuits Peripheral design enhancements ensure that non-initialized peripherals consume little current Space-critical applications benefit from the integration of commonly used system peripherals Two flexible DMA channels perform CPU-independent data transfers A flexible chip select unit simplifies memory and peripheral interfacing The interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generated from the on-chip peripherals Three general purpose timer counters round out the feature set of the 80C186EA Figure 1 shows a block diagram of the 80C186EA 80C188EA The Execution Unit (EU) is an enhanced 8086 CPU core that includes dedicated hardware to speed up effective address calculations enhance execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions string move instructions that operate at full bus bandwidth ten new instructions and static operation The Bus Interface Unit (BIU) is the same as that found on the original 80C186 family products An independent internal bus is used to allow communication between the BIU and internal peripherals 80C186EA CORE ARCHITECTURE Bus Interface Unit The 80C186EA core incorporates a bus controller that generates local bus control signals In addition it employs a HOLD HLDA protocol to share the local bus with other bus masters The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data (for write operations) information It is also responsible for reading data off the local bus during a read operation SRDY and ARDY input pins are provided to extend a bus cycle beyond the minimum four states (clocks) The local bus controller also generates two control signals (DEN and DT R) when interfacing to external transceiver chips This capability allows the addition of transceivers for simple buffering of the mulitplexed address data bus Clock Generator The processor provides an on-chip clock generator for both internal and external clock generation The clock generator features a crystal oscillator a divideby-two counter and two low-power operating modes The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-overtone mode crystal network Alternatively the oscillator circuit may be driven from an external clock source Figure 2 shows the various operating modes of the oscillator circuit The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter This counter is used to drive all internal phase clocks and the external CLKOUT signal CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components All AC timings are referenced to CLKOUT The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR (Equivalent Series Resistance) 60X max C0 (Shunt Capacitance of Crystal) 7 0 pF max CL (Load Capacitance) 20 pF g 2 pF Drive Level 2 mW max 4 4 80C186EA 80C188EA 80L186EA 80L188EA 272432 - 4 272432 - 3 (A) Crystal Connection NOTE The L1C1 network is only required when using a third-overtone crystal (B) Clock Connection Figure 2 Clock Configurations 80C186EA PERIPHERAL ARCHITECTURE The 80C186EA has integrated several common system peripherals with a CPU core to create a compact yet powerful system The integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e g the interrupt control unit supports interrupt requests from the timer counters or DMA channels) The list of integrated peripherals include Interrupt Control Unit The 80C186EA can receive interrupts from a number of sources both internal and external The Interrupt Control Unit (ICU) serves to merge these requests on a priority basis for individual service by the CPU Each interrupt source can be independently masked by the Interrupt Control Unit or all interrupts can be globally masked by the CPU Internal interrupt sources include the Timers and DMA channels External interrupt sources come from the four input pins INT3 0 The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU Although the timers only have one request input to the ICU separate vector types are generated to service individual interrupts within the Timer Unit 4-Input Interrupt Control Unit 3-Channel Timer Counter Unit 2-Channel DMA Unit 13-Output Chip-Select Unit Refresh Control Unit Power Management logic Timer Counter Unit The 80C186EA Timer Counter Unit (TCU) provides three 16-bit programmable timers Two of these are highly flexible and are connected to external pins for control or clocking A third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events generate non-repetitive waveforms generate timed interrupts etc The registers associated with each integrated periheral are contained within a 128 x 16 register file called the Peripheral Control Block (PCB) The PCB can be located in either memory or I O space on any 256 byte address boundary Figure 3 provides a list of the registers associated with the PCB when the processor's Interrupt Control Unit is in Master Mode In Slave Mode the definitions of some registers change Figure 4 provides register definitions specific to Slave Mode 5 5 80C186EA 80C188EA 80L186EA 80L188EA PCB Offset 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved End of Interrupt Poll Poll Status Interrupt Mask Priority Mask In-Service Interrupt Request Interrupt Status Timer Control DMA0 Int Control DMA1 Int Control INT0 Control INT1 Control INT2 Control INT3 Control PCB Offset 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Timer 0 Count PCB Offset 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH A0H A2H A4H A6H A8H AAH ACH AEH B0H B2H B4H B6H B8H BAH BCH BEH Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UMCS LMCS PACS MMCS MPCS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCB Offset C0H C2H C4H C6H C8H CAH CCH CEH D0H D2H D4H D6H D8H DAH DCH DEH E0H E2H E4H E6H E8H EAH ECH EEH F0H F2H F4H F6H F8H FAH FCH FEH Function DMA0 Src Lo DMA0 Src Hi DMA0 Dest Lo DMA0 Dest Hi DMA0 Count DMA0 Control Reserved Reserved DMA1 Src Lo DMA1 Src Hi DMA1 Dest Lo DMA1 Dest Hi DMA1 Count DMA1 Control Reserved Reserved Refresh Base Refresh Time Refresh Control Reserved Reserved Reserved Reserved Reserved Power-Save Power Control Reserved Step ID Reserved Reserved Reserved Relocation 52H Timer 0 Compare A 54H Timer 0 Compare B 56H 58H Timer 0 Control Timer 1 Count 5AH Timer 1 Compare A 5CH Timer 1 Compare B 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H 7AH 7CH 7EH Timer 1 Control Timer 2 Count Timer 2 Compare Reserved Timer 2 Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Figure 3 Peripheral Control Block Registers 6 6 80C186EA 80C188EA 80L186EA 80L188EA PCB Offset 20H 22H 24H 26H 28H 2AH 2C 2E 30 32 34 36 38 3A 3C 3E Function Interrupt Vector Specific EOI Reserved Reserved Interrupt Mask Priority Mask In-Service Interrupt Request Interrupt Status TMR0 Interrupt Control DMA0 Interrupt Control DMA1 Interrupt Control TMR1 Interrupt Control TMR2 Interrupt Control Reserved Reserved Chip-Select Unit The 80C186EA Chip-Select Unit integrates logic which provides up to 13 programmable chip-selects to access both memories and peripherals In addition each chip-select can be programmed to automatically terminate a bus cycle independent of the condition of the SRDY and ARDY input pins The chip-select lines are available for all memory and I O bus cycles whether they are generated by the CPU the DMA unit or the Refresh Control Unit Refresh Control Unit The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed A 9-bit counter controls the number of clocks between refresh requests A 9-bit address generator is maintained by the RCU with the address presented on the A9 1 address lines during the refresh bus cycle Address bits A19 13 are programmable to allow the refresh address block to be located on any 8 Kbyte boundary Figure 4 80C186EA Slave Mode Peripheral Control Block Registers Power Management The 80C186EA has three operational modes to control the power consumption of the device They are Power Save Mode Idle Mode and Powerdown Mode Power Save Mode divides the processor clock by a programmable value to take advantage of the fact that current is linearly proportional to frequency An unmasked interrupt NMI or reset will cause the 80C186EA to exit Power Save Mode Idle Mode freezes the clocks of the Execution Unit and the Bus Interface Unit at a logic zero state while all peripherals operate normally Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator All internal registers hold their values provided VCC is maintained Current consumption is reduced to transistor leakage only DMA Control Unit The 80C186EA DMA Contol Unit provides two independent high-speed DMA channels Data transfers can occur between memory and I O space in any combination memory to memory memory to I O I O to I O or I O to memory Data can be transferred either in bytes or words Transfers may proceed to or from either even or odd addresses but even-aligned word transfers proceed at a faster rate Each data transfer consumes two bus cycles (a minimum of eight clocks) one cycle to fetch data and the other to store data The chip-select ready logic may be programmed to point to the memory or I O space subject to DMA transfers in order to provide hardware chip select lines DMA cycles run at higher priority than general processor execution cycles 7 7 80C186EA 80C188EA 80L186EA 80L188EA The 80-lead QFP (EIAJ) pinouts are different between the 80C186XL and the 80C186EA In addition to the PDTMR pin the 80C186EA has more power and ground pins and the overall arrangement of pins was shifted A new circuit board layout for the 80C186EA is required 80C187 Interface (80C186EA Only) The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions Connecting the 80C186EA RESOUT and TEST BUSY pins to the 80C187 enables Numerics Mode operation In Numerics Mode three of the four MidRange Chip Select (MCS) pins become handshaking pins for the interface The exchange of data and control information proceeds through four dedicated I O ports If an 80C187 is not present the 80C186EA configures itself for regular operation at reset NOTE The 80C187 is not specified for 3V operation and therefore does not interface directly to the 80L186EA Operating Modes The 80C186XL has two operating modes Compatible and Enhanced Compatible Mode is a pin-to-pin replacement for the NMOS 80186 except for numerics coprocessing In Enhanced Mode the processor has a Refresh Control Unit the Power-Save feature and an interface to the 80C187 Numerics Coprocessor The MCS0 MCS1 and MCS3 pins change their functions to constitute handshaking pins for the 80C187 The 80C186EA allows all non-80C187 users to use all the MCS pins for chip-selects In regular operation all 80C186EA features (including those of the Enhanced Mode 80C186) are present except for the interface to the 80C187 Numerics Mode disables the three chip-select pins and reconfigures them for connection to the 80C187 ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system the 80C186EA has a test mode available which forces all output and input output pins to be placed in the high-impedance state ONCE stands for ``ON Circuit Emulation'' The ONCE mode is selected by forcing the UCS and LCS pins LOW (0) during a processor reset (these pins are weakly held to a HIGH (1) level) while RESIN is active TTL vs CMOS Inputs The inputs of the 80C186EA are rated for CMOS switching levels for improved noise immunity but the 80C186XL inputs are rated for TTL switching levels In particular the 80C186EA requires a minimum VIH of 3 5V to recognize a logic one while the 80C186XL requires a minimum VIH of only 1 9V (assuming 5 0V operation) The solution is to drive the 80C186EA with true CMOS devices such as those from the HC and AC logic families or to use pullup resistors where the added current draw is not a problem DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA The 80C186EA is intended as a direct functional upgrade for 80C186XL designs In many cases it will be possible to replace an existing 80C186XL with little or no hardware redesign The following sections describe differences in pinout operating modes and AC and DC specifications to keep in mind Timing Specifications 80C186EA timing relationships are expressed in a simplified format over the 80C186XL The AC performance of an 80C186EA at a specified frequency will be very close to that of an 80C186XL at the same frequency Check the timings applicable to your design prior to replacing the 80C186XL Pinout Compatibility The 80C186EA requires a PDTMR pin to time the processor's exit from Powerdown Mode The original pin arrangement for the 80C186XL in the PLCC package did not have any spare leads to use for PDTMR so the DT R pin was sacrificed The arrangement of all the other leads in the 68-lead PLCC is identical between the 80C186XL and the 80C186EA DT R may be synthesized by latching the S1 status output Therefore upgrading a PLCC 80C186XL to PLCC 80C186EA is straightforward 8 8 80C186EA 80C188EA 80L186EA 80L188EA input output (I O) Some pins have multiplexed functions (for example A19 S6) Additional symbols indicate additional characteristics for each pin Table 3 lists all the possible symbols for this column The Input Type column indicates the type of input (asynchronous or synchronous) Asynchronous pins require that setup and hold times be met only in order to guarantee recognition at a particular clock edge Synchronous pins require that setup and hold times be met to guarantee proper operation For example missing the setup or hold time for the SRDY pin (a synchronous input) will result in a system failure or lockup Input pins may also be edge- or level-sensitive The possible characteristics for input pins are S(E) S(L) A(E) and A(L) The Output States column indicates the output state as a function of the device operating mode Output states are dependent upon the current activity of the processor There are four operational states that are different from regular operation bus hold reset Idle Mode and Powerdown Mode Appropriate characteristics for these states are also indicated in this column with the legend for all possible characteristics in Table 2 The Pin Description column contains a text description of each pin As an example consider AD15 0 I O signifies the pins are bidirectional S(L) signifies that the input function is synchronous and level-sensitive H(Z) signifies that as outputs the pins are high-impedance upon acknowledgement of bus hold R(Z) signifies that the pins float during reset P(X) signifies that the pins retain their states during Powerdown Mode PACKAGE INFORMATION This section describes the pins pinouts and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Carrier (PLCC) package Shrink Quad Flat Pack (SQFP) and Quad Flat Pack (QFP) package For complete package specifications and information see the Intel Packaging Outlines and Dimensions Guide (Order Number 231369) With the extended temperature range operational characteristics are guaranteed over a temperature range corresponding to b 40 C to a 85 C ambient Package types are identified by a two-letter prefix to the part number The prefixes are listed in Table 1 Table 1 Prefix Identification Prefix Note TN TS SB N S 1 1 1 Package Type PLCC Temperature Range Extended QFP (EIAJ) Extended SQFP PLCC Extended Commercial Commercial QFP (EIAJ) Commercial NOTE 1 The 25 MHz version is only available in commercial temperature range corresponding to 0 C to a 70 C ambient Pin Descriptions Each pin or logical set of pins is described in Table 3 There are three columns for each entry in the Pin Description Table The Pin Name column contains a mnemonic that describes the pin function Negation of the signal name (for example RESIN) denotes a signal that is active low The Pin Type column contains two kinds of information The first symbol indicates whether a pin is power (P) ground (G) input only (I) output only (O) or 9 9 80C186EA 80C188EA 80L186EA 80L188EA Table 2 Pin Description Nomenclature Symbol P G I O IO S(E) S(L) A(E) A(L) H(1) H(0) H(Z) H(Q) H(X) R(WH) R(1) R(0) R(Z) R(Q) R(X) I(1) I(0) I(Z) I(Q) I(X) P(1) P(0) P(Z) P(Q) P(X) Description Power Pin (Apply a VCC Voltage) Ground (Connect to VSS) Input Only Pin Output Only Pin Input Output Pin Synchronous Edge Sensitive Synchronous Level Sensitive Asynchronous Edge Sensitive Asynchronous Level Sensitive Output Driven to VCC during Bus Hold Output Driven to VSS during Bus Hold Output Floats during Bus Hold Output Remains Active during Bus Hold Output Retains Current State during Bus Hold Output Weakly Held at VCC during Reset Output Driven to VCC during Reset Output Driven to VSS during Reset Output Floats during Reset Output Remains Active during Reset Output Retains Current State during Reset Output Driven to VCC during Idle Mode Output Driven to VSS during Idle Mode Output Floats during Idle Mode Output Remains Active during Idle Mode Output Retains Current State during Idle Mode Output Driven to VCC during Powerdown Mode Output Driven to VSS during Powerdown Mode Output Floats during Powerdown Mode Output Remains Active during Powerdown Mode Output Retains Current State during Powerdown Mode 10 10 80C186EA 80C188EA 80L186EA 80L188EA Table 3 Pin Descriptions Pin Name VCC VSS CLKIN Pin Type P G I A(E) Input Type Output States Description POWER connections consist of six pins which must be shorted externally to a VCC board plane GROUND connections consist of five pins which must be shorted externally to a VSS board plane CLocK INput is an input for an external clock An external oscillator operating at two times the required processor operating frequency can be connected to CLKIN For crystal operation CLKIN (along with OSCOUT) are the crystal connections to an internal Pierce oscillator H(Q) R(Q) P(Q) OSCillator OUTput is only used when using a crystal to generate the external clock OSCOUT (along with CLKIN) are the crystal connections to an internal Pierce oscillator This pin is not to be used as 2X clock output for non-crystal applications (i e this pin is N C for non-crystal applications) OSCOUT does not float in ONCE mode CLocK OUTput provides a timing reference for inputs and outputs of the processor and is one-half the input clock (CLKIN) frequency CLKOUT has a 50% duty cycle and transistions every falling edge of CLKIN RESet IN causes the processor to immediately terminate any bus cycle in progress and assume an initialized state All pins will be driven to a known state and RESOUT will also be driven active The rising edge (low-to-high) transition synchronizes CLKOUT with CLKIN before the processor begins fetching opcodes at memory location 0FFFF0H H(0) R(1) P(0) A(L) H(WH) R(Z) P(1) RESet OUTput that indicates the processor is currently in the reset state RESOUT will remain active as long as RESIN remains active When tied to the TEST BUSY pin RESOUT forces the 80C186EA into Numerics Mode Power-Down TiMeR pin (normally connected to an external capacitor) that determines the amount of time the processor waits after an exit from power down before resuming normal operation The duration of time required will depend on the startup characteristics of the crystal oscillator Non-Maskable Interrupt input causes a Type 2 interrupt to be serviced by the CPU NMI is latched internally TEST BUSY is sampled upon reset to determine whether the 80C186EA is to enter Numerics Mode In regular operation the pin is TEST TEST is used during the execution of the WAIT instruction to suspend CPU operation until the pin is sampled active (low) In Numerics Mode the pin is BUSY BUSY notifies the 80C186EA of 80C187 Numerics Coprocessor activity H(Z) R(Z) P(X) These pins provide a multiplexed Address and Data bus During the address phase of the bus cycle address bits 0 through 15 (0 through 7 on the 8-bit bus versions) are presented on the bus and can be latched using ALE 8- or 16-bit data information is transferred during the data phase of the bus cycle OSCOUT O CLKOUT O H(Q) R(Q) P(Q) A(L) RESIN I RESOUT O PDTMR IO NMI I A(E) TEST BUSY (TEST) I A(E) AD15 0 (AD7 0) IO S(L) NOTE Pin names in parentheses apply to the 80C188EA and 80L188EA 11 11 80C186EA 80C188EA 80L186EA 80L188EA Table 3 Pin Descriptions (Continued) Pin Name A18 16 A19 S6-A16 (A19-A8) Pin Type O Input Type Output States H(Z) R(Z) P(X) Description These pins provide multiplexed Address during the address phase of the bus cycle Address bits 16 through 19 are presented on these pins and can be latched using ALE A18 16 are driven to a logic 0 during the data phase of the bus cycle On the 8-bit bus versions A15 - A8 provide valid address information for the entire bus cycle Also during the data phase S6 is driven to a logic 0 to indicate a CPU-initiated bus cycle or logic 1 to indicate a DMA-initiated bus cycle or a refresh cycle Bus cycle Status are encoded on these pins to provide bus transaction information S2 0 are encoded as follows S2 0 0 0 0 1 1 1 1 ALE QS0 O H(0) R(0) P(0) H(Z) R(Z) P(X) S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge Read I O Write I O Processor HALT Queue Instruction Fetch Read Memory Write Memory Passive (no bus activity) S2 0 O H(Z) R(Z) P(1) Address Latch Enable output is used to strobe address information into a transparent type latch during the address phase of the bus cycle In Queue Status Mode QS0 provides queue status information along with QS1 Byte High Enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus BHE and A0 have the following logical encoding A0 0 0 1 1 BHE 0 1 0 1 Encoding (For 80C186EA 80L186EA Only) Word Transfer Even Byte Transfer Odd Byte Transfer Refresh Operation BHE (RFSH) O On the 80C188EA 80L188EA RFSH is asserted low to indicate a Refresh bus cycle RD QSMD O H(Z) R(WH) P(1) ReaD output signals that the accessed memory or I O device must drive data information onto the data bus Upon reset this pin has an alternate function As QSMD it enables Queue Status Mode when grounded In Queue Status Mode the ALE QS0 and WR QS1 pins provide the following information about processor instruction queue interaction QS1 0 0 1 1 NOTE Pin names in parentheses apply to the 80C188EA and 80L188EA QS0 0 1 1 0 Queue Operation No Queue Operation First Opcode Byte Fetched from the Queue Subsequent Byte Fetched from the Queue Empty the Queue 12 12 80C186EA 80C188EA 80L186EA 80L188EA Table 3 Pin Descriptions (Continued) Pin Name WR QS1 Pin Type O Input Type Output States H(Z) R(Z) P(1) A(L) S(L) Description WRite output signals that data available on the data bus are to be written into the accessed memory or I O device In Queue Status Mode QS1 provides queue status information along with QS0 Asychronous ReaDY is an input to signal for the end of a bus cycle ARDY is asynchronous on rising CLKOUT and synchronous on falling CLKOUT ARDY or SRDY must be active to terminate any processor bus cycle unless they are ignored due to correct programming of the Chip Select Unit Synchronous ReaDY is an input to signal for the end of a bus cycle ARDY or SRDY must be active to terminate any processor bus cycle unless they are ignored due to correct programming of the Chip Select Unit Data ENable output to control the enable of bidirectional transceivers when buffering a system DEN is active only when data is to be transferred on the bus H(Z) R(Z) P(X) H(Z) R(WH) P(1) A(L) Data Transmit Receive output controls the direction of a bidirectional buffer in a buffered system DT R is only available on the QFP (EIAJ) package and the SQFP package LOCK output indicates that the bus cycle in progress is not to be interrupted The processor will not service other bus requests (such as HOLD) while LOCK is active This pin is configured as a weakly held high input while RESIN is active and must not be driven low HOLD request input to signal that an external bus master wishes to gain control of the local bus The processor will relinquish control of the local bus between instruction boundaries not conditioned by a LOCK prefix H(1) R(0) P(0) H(1) R(1) P(1) HoLD Acknowledge output to indicate that the processor has relinquished control of the local bus When HLDA is asserted the processor will (or has) floated its data bus and control signals allowing another bus master to drive the signals directly Upper Chip Select will go active whenever the address of a memory or I O bus cycle is within the address limitations programmed by the user After reset UCS is configured to be active for memory accesses between 0FFC00H and 0FFFFFH During a processor reset UCS and LCS are used to enable ONCE Mode Lower Chip Select will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user LCS is inactive after a reset During a processor reset UCS and LCS are used to enable ONCE Mode ARDY I SRDY I S(L) DEN O H(Z) R(Z) P(1) DT R O LOCK O HOLD I HLDA O UCS O LCS O H(1) R(1) P(1) NOTE Pin names in parentheses apply to the 80C188EA and 80L188EA 13 13 80C186EA 80C188EA 80L186EA 80L188EA Table 3 Pin Descriptions (Continued) Pin Name MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NCS Pin Type IO Input Type A(L) Output States H(1) R(1) P(1) Description These pins provide a multiplexed function If enabled these pins normally comprise a block of Mid-Range Chip Select outputs which will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user In Numerics Mode (80C186EA only) three of the pins become handshaking pins for the 80C187 The CoProcessor REQuest input signals that a data transfer is pending ERROR is an input which indicates that the previous numerics coprocessor operation resulted in an exception condition An interrupt Type 16 is generated when ERROR is sampled active at the beginning of a numerics operation Numerics Coprocessor Select is an output signal generated when the processor accesses the 80C187 Peripheral Chip Selects go active whenever the address of a memory or I O bus cycle is within the address limitations programmed by the user These pins provide a multiplexed function As additional Peripheral Chip Selects they go active whenever the address of a memory or I O bus cycle is within the address limitations by the user They may also be programmed to provide latched Address A2 1 signals Timer OUTput pins can be programmed to provide a single clock or continuous waveform generation depending on the timer mode selected Timer INput is used either as clock or control signals depending on the timer mode selected DMA ReQuest is asserted by an external request when it is prepared for a DMA transfer Maskable INTerrupt input will cause a vector to a specific Type interrupt routine To allow interrupt expansion INT0 and or INT1 can be used with INTA0 and INTA1 to interface with an external slave controller INT1 becomes SELECT when the ICU is configured for Slave Mode H(1) R(Z) P(1) These pins provide multiplexed functions As inputs they provide a maskable INTerrupt that will cause the CPU to vector to a specific Type interrupt routine As outputs each is programmatically controlled to provide an INTerrupt Acknowledge handshake signal to allow interrupt expansion INT3 INTA1 becomes IRQ when the ICU is configured for Slave Mode No Connect For compatibility with future products do not connect to these pins PCS4 0 O H(1) R(1) P(1) H(1) H(X) R(1) P(1) PCS5 A1 PCS6 A2 O T0OUT T1OUT T0IN T1IN DRQ0 DRQ1 INT0 INT1 SELECT O H(Q) R(1) P(Q) A(L) A(E) A(L) A(E L) I I I INT2 INTA0 INT3 INTA1 IRQ IO A(E L) NC NOTE Pin names in parentheses apply to the 80C188EA and 80L188EA 14 14 80C186EA 80C188EA 80L186EA 80L188EA 80C186EA 80C188EA (EIAJ QFP package) as viewed from the top side of the component (i e contacts facing down) Tables 8 and 9 list the 80C186EA 80C188EA pin names with package location for the 80-pin Shrink Quad Flat Pack (SQFP) component Figure 7 depicts the complete 80C186EA 80C188EA (SQFP) as viewed from the top side of the component (i e contacts facing down) 80C186EA PINOUT Tables 4 and 5 list the 80C186EA pin names with package location for the 68-pin Plastic Leaded Chip Carrier (PLCC) component Figure 9 depicts the complete 80C186EA 80L186EA pinout (PLCC package) as viewed from the top side of the component (i e contacts facing down) Tables 6 and 7 list the 80C186EA pin names with package location for the 80-pin Quad Flat Pack (EIAJ) component Figure 6 depicts the complete Table 4 PLCC Pin Names with Package Location Address Data Bus Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 A17 A18 A19 S6 Location 17 15 13 11 8 6 4 2 16 14 12 10 7 5 3 1 68 67 66 65 Bus Control Name ALE QS0 BHE (RFSH) S0 S1 S2 RD QSMD WR QS1 ARDY SRDY DEN LOCK HOLD HLDA Power Name VSS VCC Location 26 60 9 43 Location 61 64 52 53 54 62 63 55 49 39 48 50 51 Processor Control Name RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY PDTMR NMI INT0 INT1 SELECT INT2 INTA0 INT3 INTA1 IRQ Location 24 57 59 58 56 47 40 46 45 44 42 41 Name UCS LCS MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NCS PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 A1 PCS6 A2 T0OUT T0IN T1OUT T1IN DRQ0 DRQ1 IO Location 34 33 38 37 36 35 25 27 28 29 30 31 32 22 20 23 21 18 19 NOTE Pin names in parentheses apply to the 80C188EA 80L188EA 15 15 80C186EA 80C188EA 80L186EA 80L188EA Table 5 PLCC Package Location with Pin Names Location 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Name AD15 (A15) AD7 AD14 (A14) AD6 AD13 (A13) AD5 AD12 (A12) AD4 VCC AD11 (A11) AD3 AD10 (A10) AD2 AD9 (A9) AD1 AD8 (A8) AD0 Location 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name DRQ0 DRQ1 T0IN T1IN T0OUT T1OUT RESIN PCS0 VSS PCS1 PCS2 PCS3 PCS4 PCS5 A1 PCS6 A2 LCS UCS Location 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Name MCS3 NCS MCS2 MCS1 ERROR MCS0 PEREQ DEN PDTMR INT3 INTA1 IRQ INT2 INTA0 VCC INT1 SELECT INT0 NMI TEST BUSY LOCK SRDY HOLD HLDA Location 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Name S0 S1 S2 ARDY CLKOUT RESOUT OSCOUT CLKIN VSS ALE QS0 RD QSMD WR QS1 BHE (RFSH) A19 S6 A18 A17 A16 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA NOTES 272432 - 5 1 The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number 2 Pin names in parentheses apply to the 80C186EA 80L188EA Figure 5 68-Lead PLCC Pinout Diagram 16 16 80C186EA 80C188EA 80L186EA 80L188EA Table 6 QFP (EIAJ) Pin Names with Package Location Address Data Bus Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 A17 A18 A19 S6 Location 64 66 68 70 74 76 78 80 65 67 69 71 75 77 79 1 3 4 5 6 Bus Control Name ALE QS0 BHE (RFSH) S0 S1 S2 RD QSMD WR QS1 ARDY SRDY DT R DEN LOCK HOLD HLDA Location 10 7 23 22 21 9 8 20 27 37 39 28 26 25 Processor Control Name RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY PDTMR NMI INT0 INT1 SELECT INT2 INTA0 INT3 INTA1 IRQ NC Location 55 18 16 17 19 29 38 30 31 32 35 36 11 14 15 63 Name UCS LCS MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NCS PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 A1 PCS6 A2 T0OUT T0IN T1OUT T1IN DRQ0 DRQ1 IO Location 45 46 40 41 42 43 54 52 51 50 49 48 47 57 59 56 58 61 60 Power Name VSS VCC Location 12 13 24 53 62 2 33 34 44 72 73 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA 17 17 80C186EA 80C188EA 80L186EA 80L188EA Table 7 QFP (EIAJ) Package Location with Pin Names Location 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name AD15 (A15) VCC A16 A17 A18 A19 S6 BHE (RFSH) WR QS1 RD QSMD ALE QS0 NC VSS VSS NC NC CLKIN OSCOUT RESOUT CLKOUT ARDY Location 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name S2 S1 S0 VSS HLDA HOLD SRDY LOCK TEST BUSY NMI INT0 INT1 SELECT VCC VCC INT2 INTA0 INT3 INTA1 IRQ DT R PDTMR DEN MCS0 PEREQ Location 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name MCS1 ERROR MCS2 MCS3 NCS VCC UCS LCS PCS6 A2 PCS5 A1 PCS4 PCS3 PCS2 PCS1 VSS PCS0 RESIN T1OUT T0OUT T1IN T0IN DRQ1 Location 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name DRQ0 VSS NC AD0 AD8 (A8) AD1 AD9 (A9) AD2 AD10 (A10) AD3 AD11 (A11) VCC VCC AD4 AD12 (A12) AD5 AD13 (A13) AD6 AD14 (A14) AD7 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA NOTES 272432 - 6 1 The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number 2 Pin names in parentheses apply to the 80C186EA 80L188EA Figure 6 Quad Flat Pack (EIAJ) Pinout Diagram 18 18 80C186EA 80C188EA 80L186EA 80L188EA Table 8 SQFP Pin Functions with Package Location AD Bus AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 S3 A17 S4 A18 S5 A19 S6 1 3 6 8 12 14 16 18 2 5 7 9 13 15 17 19 21 22 23 24 Bus Control ALE QS0 BHE (RFSH) S0 S1 S2 RD QSMD WR QS1 ARDY SRDY DEN DT R LOCK HOLD HLDA No Connection NC NC NC NC 4 25 35 72 29 26 40 39 38 28 27 37 44 56 54 45 43 42 Processor Control RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY NMI INT0 INT1 SELECT INT2 INTA0 INT3 INTA1 PDTMR 73 34 32 33 36 46 47 48 49 52 53 55 IO UCS LCS MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NPS PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 A1 PCS6 A2 TMR IN 0 TMR IN 1 TMR OUT 0 TMR OUT 1 DRQ0 DRQ1 62 63 57 58 59 60 71 69 68 67 66 65 64 77 76 75 74 79 78 Power and Ground VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS 10 11 20 50 51 61 30 31 41 70 80 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA Table 9 SQFP Pin Locations with Pin Names 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AD0 AD8 (A8) AD1 NC AD9 (A9) AD2 AD10 (A10) AD3 AD11 (A11) VCC VCC AD4 AD12 (A12) AD5 AD13 (A13) AD6 AD14 (A14) AD7 AD15 (A15) VCC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A16 S3 A17 S4 A18 S5 A19 S6 NC BHE (RFSH) WR QS1 RD QSMD ALE QS0 VSS VSS X1 X2 RESET NC CLKOUT ARDY S2 S1 S0 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS HLDA HOLD SRDY LOCK TEST BUSY NMI INT0 INT1 SELECT VCC VCC INT2 INTA0 INT3 INTA1 DT R PDTMR DEN MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NPS 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VCC UCS LCS PCS6 A2 PCS5 A1 PCS4 PCS3 PCS2 PCS1 VSS PCS0 NC RES TMR OUT 1 TMR OUT 0 TMR IN 1 TMR IN 0 DRQ1 DRQ0 VSS NOTE Pin names in parentheses apply to the 80C186EA 80L188EA 19 19 80C186EA 80C188EA 80L186EA 80L188EA 272432 - 7 Figure 7 Shrink Quad Flat Pack (SQFP) Pinout Diagram NOTES 1 XXXXXXXXD indicates the Intel FPO number 2 Pin names in parentheses apply to the 80C188EA PACKAGE THERMAL SPECIFICATIONS The 80C186EA 80L186EA is specified for operation when TC (the case temperature) is within the range of 0 C to 85 C (PLCC package) or 0 C to 106 C (QFP-EIAJ) package TC may be measured in any environment to determine whether the processor is within the specified operating range The case temperature must be measured at the center of the top surface TA (the ambient temperature) can be calculated from iCA (thermal resistance from the case to ambient) with the following equation TA e TC - P c iCA Typical values for iCA at various airflows are given in Table 10 P (the maximum power consumption specified in watts) is calculated by using the maximum ICC as tabulated in the DC specifications and VCC of 5 5V Table 10 Thermal Resistance (iCA) at Various Airflows (in C Watt) Airflow Linear ft min (m sec) 0 200 400 600 800 1000 (0) (1 01) (2 03) (3 04) (4 06) (5 07) iCA (PLCC) iCA (QFP) iCA (SQFP) 20 20 29 66 70 25 63 21 60 5 19 59 17 58 16 5 57 80C186EA 80C188EA 80L186EA 80L188EA ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature Case Temperature under Bias Supply Voltage with Respect to VSS b 65 C to a 150 C b 65 C to a 150 C b 0 5V to a 6 5V NOTICE This data sheet contains preliminary information on new products in production It is valid for the devices indicated in the revision history The specifications are subject to change without notice Voltage on Other Pins with Respect b 0 5V to VCC a 0 5V to VSS WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability Recommended Connections Power and ground connections must be made to multiple VCC and VSS pins Every 80C186EA based circuit board should contain separate power (VCC) and ground (VSS) planes All VCC and VSS pins must be connected to the appropriate plane Pins identified as ``N C '' must not be connected in the system Decoupling capacitors should be placed near the processor The value and type of decoupling capac- itors is application and board layout dependent The processor can cause transient power surges when its output buffers transition particularly when connected to large capacitive loads Always connect any unused input pins to an appropriate signal level In particular unused interrupt pins (NMI INT3 0) should be connected to VSS to avoid unwanted interrupts Leave any unused output pin or any ``N C '' pin unconnected 21 21 80C186EA 80C188EA 80L186EA 80L188EA DC SPECIFICATIONS (80C186EA 80C188EA) Symbol VCC VIL VIH VOL VOH VHYR IIL1 Parameter Supply Voltage Input Low Voltage for All Pins Input High Voltage for All Pins Output Low Voltage Output High Voltage Input Hysterisis on RESIN Input Leakage Current (except RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR LOCK and TEST BUSY) Input Leakage Current (RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR LOCK and TEST BUSY Output Leakage Current Supply Current Cold (RESET) 80C186EA25 80C188EA25 80C186EA20 80C188EA20 80C186EA13 80C188EA13 Supply Current In Idle Mode 80C186EA25 80C188EA25 80C186EA20 80C188EA20 80C186EA13 80C188EA13 Supply Current In Powerdown Mode 80C186EA25 80C188EA25 80C186EA20 80C188EA20 80C186EA13 80C188EA13 Output Pin Capacitance Input Pin Capacitance 0 0 b 275 Min 45 b0 5 Max 55 0 3 VCC VCC a 0 5 0 45 Units V V V V V V Conditions 0 7 VCC VCC b 0 5 0 30 IOL e 3 mA (min) IOH e b 2 mA (min) 0V s VIN s VCC g10 mA IIL2 mA VIN e 0 7 VCC (Note 1) 0 45 s VOUT s VCC (Note 2) (Notes 3 5) IOL ICC g10 mA 105 90 65 90 70 46 100 100 100 15 15 mA mA mA mA mA mA mA mA mA pF pF IID (Note 5) IPD (Note 5) COUT CIN TF e 1 MHz (Note 4) TF e 1 MHz NOTES 1 RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR LOCK and TEST BUSY have internal pullups that are only activated during RESET Loading these pins above IOL e b275 mA will cause the processor to enter alternate modes of operation 2 Output pins are floated using HOLD or ONCE Mode 3 Measured at worst case temperature and VCC with all outputs loaded as specified in the AC Test Conditions and with the device in RESET (RESIN held low) RESET is worst case for ICC 4 Output capacitance is the capacitive load of a floating output pin 5 Operating conditions for 25 MHz are 0 C to a 70 C VCC e 5 0V g10% 22 22 80C186EA 80C188EA 80L186EA 80L188EA DC SPECIFICATIONS (80L186EA 80L188EA) Symbol VCC VIL VIH VOL VOH VHYR IIL1 Parameter Supply Voltage Input Low Voltage for All Pins Input High Voltage for All Pins Output Low Voltage Output High Voltage Input Hysterisis on RESIN Input Leakage Current (except RD QSMD UCS LCS MCS0 PEREQ MCS1 LOCK and TEST) Input Leakage Current (RD QSMD UCS LCS MCS0 MCS1 LOCK and TEST) Output Leakage Current Supply Current (RESET 5 5V) 80L186EA-13 80L186EA-8 Supply Current (RESET 2 7V) 80L186EA-13 80L186EA-8 Supply Current Idle (5 5V) 80L186EA-13 80L186EA-8 Supply Current Idle (2 7V) 80L186EA-13 80L186EA-8 Supply Current Powerdown (5 5V) 80L186EA-13 80L186EA-8 Supply Current Powerdown (2 7V) 80L186EA-13 80L186EA-8 Output Pin Capacitance Input Pin Capacitance 0 0 b 275 Min 27 b0 5 Max 55 0 3 VCC VCC a 0 5 0 45 Units V V V V V V Conditions 0 7 VCC VCC b 0 5 0 30 IOL e 1 6 mA (min) IOH e b 1 mA (min) 0V s VIN s VCC g10 mA IIL2 mA VIN e 0 7 VCC (Note 1) 0 45 s VOUT s VCC (Note 2) (Note 3) (Note 3) (Note 3) (Note 3) IOL ICC5 g10 mA 65 40 34 20 46 28 24 14 100 100 50 50 15 15 mA mA mA mA mA mA mA mA mA mA mA mA pF pF ICC3 IID5 IID5 IPD5 IPD3 COUT CIN TF e 1 MHz (Note 4) TF e 1 MHz NOTES 1 RD QSMD UCS LCS MCS0 MCS1 LOCK and TEST have internal pullups that are only activated during RESET Loading these pins above IOL e b275 mA will cause the processor to enter alternate modes of operation 2 Output pins are floated using HOLD or ONCE Mode 3 Measured at worst case temperature and VCC with all outputs loaded as specified in the AC Test Conditions and with the device in RESET (RESIN held low) 4 Output capacitance is the capacitive load of a floating output pin 23 23 80C186EA 80C188EA 80L186EA 80L188EA ICC VERSUS FREQUENCY AND VOLTAGE The current (ICC) consumption of the processor is essentially composed of two components IPD and ICCS IPD is the quiescent current that represents internal device leakage and is measured with all inputs or floating outputs at GND or VCC (no clock applied to the device) IPD is equal to the Powerdown current and is typically less than 50 mA ICCS is the switching current used to charge and discharge parasitic device capacitance when changing logic levels Since ICCS is typically much greater than IPD IPD can often be ignored when calculating ICC ICCS is related to the voltage and frequency at which the device is operating It is given by the formula Power e V c I e V2 c CDEV c f I e ICC e ICCS e V c CDEV c f e Device operating voltage (VCC) Where V CDEV e Device capacitance f e Device operating frequency ICCS e ICC e Device current Measuring CDEV on a device like the 80C186EA would be difficult Instead CDEV is calculated using the above formula by measuring ICC at a known VCC and frequency (see Table 11) Using this CDEV value ICC can be calculated at any voltage and frequency within the specified operating range EXAMPLE Calculate the typical ICC when operating at 20 MHz 4 8V ICC e ICCS e 4 8 c 0 515 c 20 49 mA PDTMR PIN DELAY CALCULATION The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal clocks when exiting Powerdown A delay is required only when using the on-chip oscillator to allow the crystal or resonator circuit time to stabilize NOTE The PDTMR pin function does not apply when RESIN is asserted (i e a device reset during Powerdown is similar to a cold reset and RESIN must remain active until after the oscillator has stabilized) To calculate the value of capacitor required to provide a desired delay use the equation 440 c t e CPD (5V 25 C) Where t e desired delay in seconds CPD e capacitive load on PDTMR in microfarads EXAMPLE To get a delay of 300 ms a capacitor value of CPD e 440 c (300 c 10b6) e 0 132 mF is required Round up to standard (available) capacitive values NOTE The above equation applies to delay times greater than 10 ms and will compute the TYPICAL capacitance needed to achieve the desired delay A delay variance of a 50% or b 25% can occur due to temperature voltage and device process extremes In general higher VCC and or lower temperature will decrease delay time while lower VCC and or higher temperature will increase delay time Table 11 CDEV Values Parameter CDEV (Device in Reset) Typ 0 515 Max 0 905 Units mA V MHz Notes 12 CDEV (Device in Idle) 0 391 0 635 mA V MHz 12 1 Max CDEV is calculated at b40 C all floating outputs driven to VCC or GND and all outputs loaded to 50 pF (including CLKOUT and OSCOUT) 2 Typical CDEV is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and OSCOUT which are not loaded 24 24 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time 80C186EA25 80C186EA20 80C186EA13 Min 0 20 10 10 1 1 0 (T 2) b 5 (T 2) b 5 1 1 3 3 3 Max 50 % % % 8 8 15 2TC 6 6 20 25 20 Min 0 25 10 10 1 1 0 (T 2) b 5 (T 2) b 5 1 1 3 3 3 Max 40 % % % 8 8 17 2 TC 6 6 22 27 22 Min 0 38 5 12 12 1 1 0 (T 2) b 5 (T 2) b 5 1 1 3 3 3 Max Units 26 % % % 8 8 23 2 TC 6 6 25 30 25 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 12 12 13 13 14 1 1 1 15 15 1467 1468 146 25 MHz(12) 20 MHz 13 MHz Parameter OUTPUT CLOCK OUTPUT DELAYS TCHOV1 ALE S2 0 DEN DT R BHE (RFSH) LOCK A19 16 TCHOV2 MCS3 0 LCS UCS PCS6 0 NCS RD WR TCLOV1 BHE (RFSH) DEN LOCK RESOUT HLDA T0OUT T1OUT A19 16 TCLOV2 RD WR MCS3 0 LCS UCS PCS6 0 AD15 0 (A15 8 AD7 0) NCS INTA1 0 S2 0 TCHOF TCLOF RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (A15 8 AD7 0) 3 25 3 27 3 30 ns 146 0 0 25 25 0 0 25 25 0 0 25 25 ns ns 1 1 25 25 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS (Continued) AC Characteristics Symbol TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH TCLIS TCLIH 80C186EA25 80C186EA20 80C186EA13 Min 8 3 10 3 10 3 10 3 Max Min 10 3 10 3 10 3 10 3 Max Min 10 3 10 3 10 3 10 3 Max Units ns ns ns ns ns ns ns ns Notes 19 19 1 10 1 10 19 19 19 19 25 MHz(12) 20 MHz 13 MHz Parameter TEST NMI INT3 0 T1 0IN ARDY TEST NMI INT3 0 T1 0IN ARDY AD15 0 (AD7 0) ARDY SRDY DRQ1 0 AD15 0 (AD7 0) ARDY SRDY DRQ1 0 HOLD PEREQ ERROR (80C186EA Only) HOLD PEREQ ERROR (80C186EA Only) RESIN (to CLKIN) RESIN (from CLKIN) SYNCHRONOUS INPUTS NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measured at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 11 TCHOVS applies to BHE (RFSH) and A19 16 only after a HOLD release 12 Operating conditions for 25 MHz are 0 C to a 70 C VCC e 5 0V g10% Pin names in parentheses apply to the 80C188EA 80L188EA 26 26 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCHOV3 TCLOV1 TCLOV2 TCLOV3 TCLOV4 TCLOV5 TCHOF CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time ALE LOCK MCS3 0 LCS UCS PCS6 0 RD WR S2 0 (DEN) DT R BHE (RFSH) A19 16 LOCK RESOUT HLDA T0OUT T1OUT RD WR MCS3 0 LCS UCS PCS6 0 INTA1 0 BHE (RFSH) DEN A19 16 AD15 0 (A15 8 AD7 0) S2 0 RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (A15 8 AD7 0) 80L186EA13 80L186EA8 Min 13 MHz 0 38 5 12 12 1 1 0 (T 2) b 5 (T 2) b 5 1 1 3 3 3 3 3 3 3 3 0 26 % % % 8 8 45 2 TC 12 12 27 32 30 27 32 30 34 38 27 Max Min 8 MHz 0 62 5 12 12 1 1 0 (T 2) b 5 (T 2) b 5 1 1 3 3 3 3 3 3 3 3 0 16 % % % 8 8 95 2 TC 12 12 27 32 30 27 35 30 35 40 27 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 12 12 13 13 14 1 1 1 15 15 1467 14 68 1 146 146 146 146 146 1 Max Units Notes Parameter OUTPUT CLOCK OUTPUT DELAYS TCLOF 0 27 0 27 ns 1 NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measured at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 11 TCHOVS applies to BHE (RFSH) and A19 16 only after a HOLD release 12 Pin names in parentheses apply to the 80C188EA 80L188EA 27 27 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS AC Characteristics Symbol SYNCHRONOUS INPUTS TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH TCLIS TCLIH TEST NMI INT3 0 T1 0IN ARDY TEST NMI INT3 0 T1 0IN ARDY AD15 0 (AD7 0) ARDY SRDY DRQ1 0 AD15 0 (AD7 0) ARDY SRDY DRQ1 0 HOLD HOLD RESIN (to CLKIN) RESIN (from CLKIN) 80L186EA13 80L186EA8 Parameter Min 22 3 22 3 22 3 22 3 Max Min 22 3 22 3 22 3 22 3 Max Units ns ns ns ns ns ns ns ns Notes 19 19 1 10 1 10 19 19 19 19 13 MHz 8 MHz NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measured at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 11 TCHOVS applies to BHE (RFSH) and A19 16 only after a HOLD release 12 Pin names in parentheses apply to the 80C188EA 80L188EA 28 28 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS (Continued) Relative Timings (80C186EA25 20 13 80L186EA13 8) Symbol RELATIVE TIMINGS TLHLL TAVLL TPLLL TLLAX TLLWL TLLRL TRHLH TWHLH TAFRL TRLRH TWLWH TRHAV TWHDX TWHDEX TWHPH TRHPH TPHPL TDXDL TOVRH TRHOX ALE Rising to ALE Falling Address Valid to ALE Falling Chip Selects Valid to ALE Falling Address Hold from ALE Falling ALE Falling to WR Falling ALE Falling to RD Falling RD Rising to ALE Rising WR Rising to ALE Rising Address Float to RD Falling RD Falling to RD Rising WR Falling to WR Rising RD Rising to Address Active Output Data Hold after WR Rising WR Rising to DEN Rising WR Rising to Chip Select Rising RD Rising to Chip Select Rising CS Inactive to CS Active DEN Inactive to DT R Low ONCE (UCS LCS) Active to RESIN Rising ONCE (UCS LCS) to RESIN Rising T b 15 T b 10 T b 10 T b 10 T b 15 T b 15 T b 10 T b 10 0 (2 T) b 5 (2 T) b 5 T b 15 T b 15 T b 10 T b 10 T b 10 T b 10 0 T T ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 14 14 1 5 3 3 2 2 1 1 1 1 1 Parameter Min Max Unit Notes NOTES 1 Assumes equal loading on both pins 2 Can be extended using wait states 3 Not tested 4 Not applicable to latched A2 1 These signals change only on falling T1 5 For write cycle followed by read cycle 6 Operating conditions for 25 MHz are 0 C to a 70 C VCC e 5 0V g10% 29 29 80C186EA 80C188EA 80L186EA 80L188EA AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 8 See the Derating Curves section to see how timings vary with load capacitance CL e 50 pF for all signals 272432 - 8 Specifications are measured at the VCC 2 crossing point unless otherwise specified See AC Timing Waveforms for AC specification definitions test pins and illustrations Figure 8 AC Test Load AC TIMING WAVEFORMS 272432 - 9 Figure 9 Input and Output Clock Waveform 30 30 80C186EA 80C188EA 80L186EA 80L188EA 272432 - 10 NOTE 20% VCC k Float k 80% VCC Figure 10 Output Delay and Float Waveform 272432 - 11 NOTE RESIN measured to CLKIN not CLKOUT Figure 11 Input Setup and Hold 31 31 80C186EA 80C188EA 80L186EA 80L188EA 272432 - 12 NOTES 1 TDXDL for write cycle followed by read cycle 2 Pin names in parentheses apply to tthe 80C188EA Figure 12 Relative Signal Waveform 32 32 80C186EA 80C188EA 80L186EA 80L188EA DERATING CURVES 272432 - 13 272432 - 14 Figure 13 Typical Output Delay Variations Versus Load Capacitance Figure 14 Typical Rise and Fall Variations Versus Load Capacitance must ensure that the ramp time for VCC is not so long that RESIN is never really sampled at a logic low level when VCC reaches minimum operating conditions Figure 16 shows the timing sequence when RESIN is applied after VCC is stable and the device has been operating Note that a reset will terminate all activity and return the processor to a known operating state Any bus operation that is in progress at the time RESIN is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating) While RESIN is active signals RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR LOCK and TEST BUSY are configured as inputs and weakly held high by internal pullup transistors Forcing UCS and LCS low selects ONCE Mode Forcing QSMD low selects Queue Status Mode Forcing TEST BUSY high at reset and low four clocks later enables Numerics Mode Forcing LOCK low is prohibited and results in unspecified operation RESET The processor performs a reset operation any time the RESIN pin is active The RESIN pin is actually synchronized before it is presented internally which means that the clock must be operating before a reset can take effect From a power-on state RESIN must be held active (low) in order to guarantee correct initialization of the processor Failure to provide RESIN while the device is powering up will result in unspecified operation of the device Figure 15 shows the correct reset sequence when first applying power to the processor An external clock connected to CLKIN must not exceed the VCC threshold being applied to the processor This is normally not a problem if the clock driver is supplied with the same VCC that supplies the processor When attaching a crystal to the device RESIN must remain active until both VCC and CLKOUT are stable (the length of time is application specific and depends on the startup characteristics of the crystal circuit) The RESIN pin is designed to operate correctly using an RC reset circuit but the designer 33 33 34 272432- 15 80C186EA 80C188EA 80L186EA 80L188EA Figure 15 Powerup Reset Waveforms NOTES 1 CLKOUT synchronization occurs approximately 1 CLKIN periods after RESIN is sampled low 2 Pin names in parentheses apply to the 80C188EA 34 Figure 16 Warm Reset Waveforms 272432- 16 80C186EA 80C188EA 80L186EA 80L188EA NOTES 1 CLKOUT resynchronization occurs approximately 1 CLKIN periods after RESIN is sampled low If RESIN is sampled low while CLKOUT is transitioning high then CLKOUT will remain high for two CLKIN periods If RESIN is sampled low while CLKOUT is transitioning high then CLKOUT will not be affected 2 Pin names in parentheses apply to the 80C188EA 35 35 80C186EA 80C188EA 80L186EA 80L188EA BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cycles that are generated by the processor What is shown in the figure is the relationship of the various bus signals to CLKOUT These figures along with the information present in AC Specifications allow the user to determine all the critical timing analysis needed for a given application 272432-17 NOTES 1 During the data phase of the bus cycle A19 S6 is driven high for a DMA or refresh cycle 2 Pin names in parentheses apply to the 80C188EA Figure 17 Read Fetch and Refresh Cycle Waveform 36 36 80C186EA 80C188EA 80L186EA 80L188EA 272432-18 NOTES 1 During the data phase of the bus cycle A19 S6 is driven high for a DMA cycle 2 Pin names in parentheses apply to the 80C188EA Figure 18 Write Cycle Waveform 37 37 80C186EA 80C188EA 80L186EA 80L188EA 272432 - 19 NOTES 1 The processor drives these pins to 0 during Idle and Powerdown Modes 2 Pin names in parentheses apply to the 80C188EA Figure 19 Halt Cycle Waveform 38 38 80C186EA 80C188EA 80L186EA 80L188EA NOTES 1 INTA occurs one clock later in Slave Mode 2 Pin names in parentheses apply to the 80C188EA 272432 - 20 Figure 20 INTA Cycle Waveform 39 39 80C186EA 80C188EA 80L186EA 80L188EA 272432 - 21 NOTE 1 Pin names in parentheses apply to the 80C188EA Figure 21 HOLD HLDA Waveform 40 40 80C186EA 80C188EA 80L186EA 80L188EA 272432 - 22 NOTE 1 Pin names in parentheses apply to the 80C188EA Figure 22 DRAM Refresh Cycle During Hold Acknowledge 41 41 80C186EA 80C188EA 80L186EA 80L188EA 272432 - 23 NOTES 1 Generalized diagram for READ or WRITE 2 ARDY low by either edge causes a wait state Only rising ARDY is fully synchronized 3 SRDY low causes a wait state SRDY must meet setup and hold times to ensure correct device operation 4 Either ARDY or SRDY active high will terminate a bus cycle 5 Pin names in parentheses apply to the 80C188EA Figure 23 Ready Waveform 42 42 80C186EA 80C188EA 80L186EA 80L188EA All instructions which involve memory accesses can require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit With a 16-bit BIU the 80C186EA has sufficient bus performance to endure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time Therefore actual program exeuction time will not be substanially greater than that derived from adding the instruction timings shown The 80C188EA 8-bit BIU is limited in its performance relative to the execution unit A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time Therefore actual program execution time will be substantially greater than that derived from adding the instruction timings shown 80C186EA 80C188EA EXECUTION TIMINGS A determination of program exeuction timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions The following instruction timings represent the minimum execution time in clock cycle for each instruction The timings given are based on the following assumptions The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed No wait states or bus HOLDs occur All word-data is located on even-address boundaries (80C186EA only) All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address 43 43 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV e Move Register to Register Memory Register memory to register Immediate to register memory Immediate to register Memory to accumulator Accumulator to memory Register memory to segment register Segment register to register memory PUSH e Push Memory Register Segment register Immediate PUSHA e Push All POP e Pop Memory Register Segment register POPA e Pop All XCHG e Exchange Register memory with register Register with accumulator IN e Input from Fixed port Variable port OUT e Output to Fixed port Variable port XLAT e Translate byte to AL LEA e Load EA to register LDS e Load pointer to DS LES e Load pointer to ES LAHF e Load AH with flags SAHF e Store AH into flags PUSHF e Push flags POPF e Pop flags 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r m mod reg r m mod reg r m (mod i 11) (mod i 11) port 9 7 11 6 18 18 2 3 9 8 9 7 15 6 26 26 2 3 13 12 1110010w 1110110w port 10 8 10 7 1000011w 1 0 0 1 0 reg mod reg r m 4 17 3 4 17 3 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 01100001 (reg i 01) mod 0 0 0 r m 20 10 8 51 24 14 12 83 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 011010s0 01100000 data data if s e 0 mod 1 1 0 r m 16 10 9 10 36 20 14 13 14 68 1000100w 1000101w 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 mod reg r m mod reg r m mod 000 r m data addr-low addr-low mod 0 reg r m mod 0 reg r m data data if w e 1 addr-high addr-high data if w e 1 2 12 29 12-13 3-4 8 9 29 2 11 2 12 29 12-13 3-4 8 9 2 13 2 15 8 16-bit 8 16-bit Format 80C186EA Clock Cycles 80C188EA Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 44 44 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY (Continued) Function DATA TRANSFER (Continued) SEGMENT e Segment Override CS SS DS ES ARITHMETIC ADD e Add Reg memory with register to either Immediate to register memory Immediate to accumulator ADC e Add with carry Reg memory with register to either Immediate to register memory Immediate to accumulator INC e Increment Register memory Register SUB e Subtract Reg memory and register to either Immediate from register memory Immediate from accumulator SBB e Subtract with borrow Reg memory and register to either Immediate from register memory Immediate from accumulator DEC e Decrement Register memory Register CMP e Compare Register memory with register Register with register memory Immediate with register memory Immediate with accumulator NEG e Change sign register memory AAA e ASCII adjust for add DAA e Decimal adjust for add AAS e ASCII adjust for subtract DAS e Decimal adjust for subtract MUL e Multiply (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word 0011101w 0011100w 100000sw 0011110w 1111011w 00110111 00100111 00111111 00101111 1111011w mod 100 r m 26-28 35-37 32-34 41-43 26-28 35-37 32-34 41-48 mod reg r m mod reg r m mod 1 1 1 r m data mod 0 1 1 r m data data if w e 1 data if s w e 01 3 10 3 10 3 10 34 3 10 8 4 7 4 3 10 3 10 3 10 34 3 10 8 4 7 4 8 16-bit 1111111w 0 1 0 0 1 reg mod 0 0 1 r m 3 15 3 3 15 3 000110dw 100000sw 0001110w mod reg r m mod 0 1 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 001010dw 100000sw 0010110w mod reg r m mod 1 0 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 1111111w 0 1 0 0 0 reg mod 0 0 0 r m 3 15 3 3 15 3 000100dw 100000sw 0001010w mod reg r m mod 0 1 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 000000dw 100000sw 0000010w mod reg r m mod 0 0 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 00101110 00110110 00111110 00100110 2 2 2 2 2 2 2 2 Format 80C186EA Clock Cycles 80C188EA Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 45 45 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY (Continued) Function ARITHMETIC (Continued) IMUL e Integer multiply (signed) Register-Byte Register-Word Memory-Byte Memory-Word IMUL e Integer Immediate multiply (signed) DIV e Divide (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word IDIV e Integer divide (signed) Register-Byte Register-Word Memory-Byte Memory-Word AAM e ASCII adjust for multiply AAD e ASCII adjust for divide CBW e Convert byte to word CWD e Convert word to double word LOGIC Shift Rotate Instructions Register Memory by 1 Register Memory by CL Register Memory by Count 1101000w 1101001w 1100000w mod TTT r m mod TTT r m mod TTT r m TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL SAL 101 SHR 111 SAR AND e And Reg memory and register to either Immediate to register memory Immediate to accumulator TEST e And function to flags no result Register memory and register Immediate data and register memory Immediate data and accumulator OR e Or Reg memory and register to either Immediate to register memory Immediate to accumulator 000010dw 1000000w 0000110w mod reg r m mod 0 0 1 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit 1000010w 1111011w 1010100w mod reg r m mod 0 0 0 r m data data data if w e 1 data if w e 1 3 10 4 10 34 3 10 4 10 34 8 16-bit 001000dw 1000000w 0010010w mod reg r m mod 1 0 0 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit count 2 15 2 15 11010100 11010101 10011000 10011001 00001010 00001010 1111011w mod 1 1 1 r m 44-52 53-61 50-58 59-67 19 15 2 4 44-52 53-61 50-58 59-67 19 15 2 4 011010s1 mod reg r m data data if s e 0 1111011w mod 1 0 1 r m 25-28 34-37 31-34 40-43 22-25 29-32 25-28 34-37 32-34 40-43 22-25 29-32 Format 80C186EA Clock Cycles 80C188EA Clock Cycles Comments 1111011w mod 1 1 0 r m 29 38 35 44 29 38 35 44 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 46 46 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY (Continued) Function LOGIC (Continued) XOR e Exclusive or Reg memory and register to either Immediate to register memory Immediate to accumulator NOT e Invert register memory STRING MANIPULATION MOVS e Move byte word CMPS e Compare byte word SCAS e Scan byte word LODS e Load byte wd to AL AX STOS e Store byte wd from AL AX INS e Input byte wd from DX port OUTS e Output byte wd to DX port 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 14 22 15 12 10 14 14 14 22 15 12 10 14 14 001100dw 1000000w 0011010w 1111011w mod reg r m mod 1 1 0 r m data mod 0 1 0 r m data data if w e 1 data if w e 1 3 10 4 16 34 3 10 3 10 4 16 34 3 10 8 16-bit Format 80C186EA Clock Cycles 80C188EA Clock Cycles Comments Repeated by count in CX (REP REPE REPZ REPNE REPNZ) MOVS e Move string CMPS e Compare string SCAS e Scan string LODS e Load string STOS e Store string INS e Input string OUTS e Output string CONTROL TRANSFER CALL e Call Direct within segment Register memory indirect within segment Direct intersegment 11101000 11111111 disp-low mod 0 1 0 r m disp-high 15 13 19 19 17 27 11110010 1111001z 1111001z 11110010 11110010 11110010 11110010 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 10011010 segment offset segment selector 23 31 Indirect intersegment JMP e Unconditional jump Short long Direct within segment Register memory indirect within segment Direct intersegment 11111111 mod 0 1 1 r m (mod i 11) 38 54 11101011 11101001 11111111 disp-low disp-low mod 1 0 0 r m disp-high 14 14 11 17 14 14 11 21 11101010 segment offset segment selector 14 14 Indirect intersegment 11111111 mod 1 0 1 r m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 47 47 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY (Continued) Function CONTROL TRANSFER (Continued) RET e Return from CALL Within segment Within seg adding immed to SP Intersegment Intersegment adding immediate to SP JE JZ e Jump on equal zero JL JNGE e Jump on less not greater or equal JLE JNG e Jump on less or equal not greater JB JNAE e Jump on below not above or equal JBE JNA e Jump on below or equal not above JP JPE e Jump on parity parity even JO e Jump on overflow JS e Jump on sign JNE JNZ e Jump on not equal not zero JNL JGE e Jump on not less greater or equal JNLE JG e Jump on not less or equal greater JNB JAE e Jump on not below above or equal JNBE JA e Jump on not below or equal above JNP JPO e Jump on not par par odd JNO e Jump on not overflow JNS e Jump on not sign JCXZ e Jump on CX zero LOOP e Loop CX times LOOPZ LOOPE e Loop while zero equal LOOPNZ LOOPNE e Loop while not zero equal ENTER e Enter Procedure Le0 Le1 Ll1 LEAVE e Leave Procedure INT e Interrupt Type specified Type 3 INTO e Interrupt on overflow 11001101 11001100 11001110 type 47 45 48 4 47 45 48 4 if INT taken if INT not taken 11001001 11000011 11000010 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110 000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100011 11100010 11100001 11100000 11001000 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-low data-high L 15 25 22 a 16(n b 1) 8 19 29 26 a 20(n b 1) 8 data-high data-low data-high 16 18 22 25 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 20 22 30 33 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 LOOP not taken LOOP taken JMP not taken JMP taken Format 80C186EA Clock Cycles 80C188EA Clock Cycles Comments IRET e Interrupt return BOUND e Detect value out of range 11001111 01100010 mod reg r m 28 33-35 28 33-35 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 48 48 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY (Continued) Function PROCESSOR CONTROL CLC e Clear carry CMC e Complement carry STC e Set carry CLD e Clear direction STD e Set direction CLI e Clear interrupt STI e Set interrupt HLT e Halt WAIT e Wait LOCK e Bus lock prefix NOP e No Operation 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 10010000 (TTT LLL are opcode to processor extension) 2 2 2 2 2 2 2 2 6 2 3 2 2 2 2 2 2 2 2 6 2 3 if TEST e 0 Format 80C186EA Clock Cycles 80C188EA Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers The Effective Address (EA) of the memory operand is computed according to the mod and r m fields if mod e 11 then r m is treated as a REG field if mod e 00 then DISP e 0 disp-low and disphigh are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits disp-high is absent if mod e 10 then DISP e disp-high disp-low e 000 then EA e (BX) a (SI) a DISP if r m e 001 then EA e (BX) a (DI) a DISP if r m e 010 then EA e (BP) a (SI) a DISP if r m e 011 then EA e (BP) a (DI) a DISP if r m e 100 then EA e (SI) a DISP if r m e 101 then EA e (DI) a DISP if r m e 110 then EA e (BP) a DISP if r m e 111 then EA e (BX) a DISP if r m DISP follows 2nd byte of instruction (before data if required) except if mod e 00 and r m e 110 then EA e disp-high disp-low EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenever appropriate Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table 16-Bit (w e 1) 8-Bit (w e 0) 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment register The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment which may not be overridden 49 49 80C186EA 80C188EA 80L186EA 80L188EA REVISION HISTORY Intel 80C186EA 80L186EA devices are marked with a 9-character alphanumeric Intel FPO number underneath the product number This data sheet update is valid for devices with an ``A'' ``B'' ``C'' ``D'' or ``E'' as the ninth character in the FPO number as illustrated in Figure 5 for the 68-lead PLCC package Figure 6 for the 84-lead QFP (EIAJ) package and Figure 7 for the 80-lead SQFP device Such devices may also be identified by reading a value of 01H 02H 03H from the STEPID register This data sheet replaces the following data sheets 272019-002 272020-002 272021-002 272022-002 272307-001 272308-001 80C186EA 80C188EA 80L186EA 80L188EA SB80C186EA SB80L186EA SB80C188EA SB80L188EA ERRATA An 80C186EA 80L186EA with a STEPID value of 01H or 02H has the following known errata A device with a STEPID of 01H or 02H can be visually identified by noting the presence of an ``A'' ``B'' or ``C'' alpha character next to the FPO number The FPO number location is shown in Figures 5 6 and 7 1 An internal condition with the interrupt controller can cause no acknowledge cycle on the INTA1 line in response to INT1 This errata only occurs when Interrupt 1 is configured in cascade mode and a higher priority interrupt exists This errata will not occur consistantly it is dependent on interrupt timing An 80C186EA 80L186EA with a STEPID value of 03H has no known errata A device with a STEPID of 03H can be visually identified by noting the presence of a ``D'' or ``E'' alpha character next to the FPO number The FPO number location is shown in Figures 5 6 and 7 50 50 |
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